‘Computing memory’ gains traction amid AI bottlenecks...Three DRAM makers accelerate technology development

[Financial News] Competition in memory technology in the artificial intelligence (AI) semiconductor market is expanding beyond simply increasing the bandwidth of high-bandwidth memory (HBM) toward next-generation architectures that reduce data movement. As AI models grow larger, the power consumption and bottlenecks caused by data movement are increasing. The three global memory makers are consequently introducing new technologies one after another to reduce them.
According to industry sources on the 7th, this trend was also highlighted at SEMICON Taiwan 2026, held in Taiwan earlier this month. SEMICON Taiwan is a major semiconductor event where global semiconductor companies showcase next-generation technologies, including advanced processes, packaging and memory. This year’s event featured a series of next-generation memory architectures that differ from conventional designs, such as adding computing functions directly to memory or shortening the distance between memory and computing devices.
Samsung Electronics is also accelerating the commercialization of Processing-In-Memory (PIM), which performs some computations directly inside memory. According to overseas media outlets, including DigiTimes, Samsung Electronics said at SEMICON Taiwan that it aims to begin mass production of LPDDR5X-PIM, low-power DRAM with added computing functions, by the end of this year or early next year. LPDDR5X-PIM reduces the amount of data transferred between the processor and memory by processing some operations directly inside the memory. It can improve processing performance and power efficiency by reducing the time and power consumed by data movement during AI inference.
The scope of PIM applications is also expected to expand to next-generation products. Choi Jang-seok, executive vice president and head of product planning for the Memory Business of Samsung Electronics’ Device Solutions (DS) Division, explained at the event that standardization work by the Joint Electron Device Engineering Council (JEDEC) to apply PIM to LPDDR6, a next-generation mobile DRAM, has also made substantial progress.
SK hynix presented technology that adds computing functions to HBM.
Kim Ho-sik, vice president in charge of memory systems research at SK hynix, introduced custom HBM technology with some computing functions embedded in the HBM base die at the event. The approach directly processes some operations in the base die at the bottom of HBM, reducing the repeated transfer of data between HBM and the GPU. Kim explained that applying this architecture could improve large language model (LLM) inference performance by up to 5.15 times. He added that, starting with HBM4, the use of a logic process rather than a conventional memory process for the base die creates greater room for adding various functions beyond a memory controller.
Micron Technology presented a next-generation technology that directly couples DRAM with computing devices to shorten the distance data must travel. Mark Kielbaugh, a vice president at Micron Technology, introduced the concept of Tightly Coupled DRAM, which places DRAM directly on top of logic, at the event. Micron Technology expects this architecture to deliver bandwidth more than 10 times higher than existing HBM while significantly reducing the power required for data movement.
Although their implementation methods differ, all three companies are focused on reducing bottlenecks between memory and computing devices. Samsung Electronics and SK hynix, in particular, are expanding technology development by adding computing functions to DRAM and HBM base dies, respectively, to improve AI processing performance and power efficiency.
Industry observers expect memory power efficiency to emerge as a key factor determining overall system performance as the volume of data required for AI computing grows. An industry official said, "Competition in next-generation memory technologies that combine computing functions, rather than simply increasing memory capacity and bandwidth, is expected to intensify further."

[email protected] Park Ji-yeon Reporter